This IP core has been developed to be a complete standards compliant High Speed M-JPEG Hardware Encoder. It has been implemented on several ASIC and FPGA targets.
- Baseline DCT compression (JPEG ITU-T T.81 | ISO/IEC 10918-1 with JFIF support)
- Industry standard AXI interfaces (AXI and AXI4-stream for row-wise inputs)
- Plug and Play IP blocks for Xilinx Vivado and Altera Quartus Qsys
- No need for external CPU or memory.
- On-the-fly selectable quality level/compression ratio.
- Selectable chroma subsampling (4:4:4, 4:2:2, 4:2:0).
- Unlimited input image size (up to 64K x 64K as per JPEG spec.).
- Throughput: 2 compressed pixels every 3 clock cycles (constant).
- Compared to other JPEG IP cores this is the fastest and most versatile solution.
- It allows a larger versatility thanks to its in built quality selection capability, so you can change the compression ratio and chroma subsampling before every image compression just by changing one register.
- No need for any external components (CPU, DDR, ...).
- Tailored to your very needs: Look for your part number at the core's website in order to know the exact resource requirements and maximum frequency for your FPGA part.
- Technical support
- Documentation and design examples
- Altera and Xilinx IP blocks
- Instantation Templates