The SMD103, M13 Multiplexer and De-multiplexer (M13MD), Intellectual Property (IP) block performs the functions of M13 multiplexing in the transmit direction and M13 de-multiplexing in the receive direction. The purpose of the M13 multiplexer/transmitter is to generate DS3 or E3 data channel running at 44.184 Mb/s or 34.368 Mb/s by multiplexing 28 DS1 or 21 E1 signals, respectively. Conversely, M13 de-multiplexer/receiver generates 28 DS1 or 21 E1 signals out of single DS3 signal. The Silicomotive’s M13 Multiplexer and De-multiplexer (M13MD) IP block combines the above functions and it adheres to the recommendations specified in ANSI T1.107, ITU-T G.747 and ITU-T G.751 standards.
- 28 independent DS1 clock inputs each with programmable clock edge adapter.
- 28 independent DS1 outputs each with programmable clock edge adapter.
- 7 independent DS2 framers supporting DS1 and G.747.
- 4 independent E2 framers.
- Supports M23 or C-bit parity formats.
- Supports G.747 formats for E1 to be multiplexed into a DS3.
- Interrupts can be generated on alarm events or status changes.
- Supports DS3 Activated DS2 Line Loopback.
- Supports DS2 Activated DS1 Line Loopback.
- M13MD IP block can be used to develop a single low cost, low power chip solution to address the need of M13 multiplex/de-multiplex functions or it can be used as one of many IP’s interconnected in the system on the chip (SoC) application.
- Typical applications for the M13MD support channelized DS3 with serial line interfaces on the low speed side. M13MD design allow usage in following systems/devices:
- Terminal Multiplexers with DS1/E1 and HDSL interfaces
- Add Drop Multiplexers (ADM) with DS1 E1 and HDSL interfaces
- Digital Cross Connect devices with DS1 E1 and HDSL interfaces
- Channelized DS3 applications
- The Interfaces of M13MD are designed to interface with other components in the system without need for clock tree balancing across the system. This reduces the timing problems in the large SoC devices.
- Typical placement of the M13MD block within the system is between DS3 framer and T1/E1 framers.
- Verilog RTL Source Code
- Functional testbench
- Synthesis constraints files
- Integration support