MAC 10/100/1000 Ethernet Controller

Features

• IEEE 802.3-2002 specification with preamble, start-of-frame delimiter (SFD), frame padding generation and cyclic redundancy code (CRC) generation and checking is fully implemented
• Supports 10/100 Mbps or 1000 Mbps operation (selectable via a core configuration registers)
• Supports full- and half-duplex operation (selectable via a core configuration registers)
• CSMA/CD protocol for half-duplex operation
• Supports frame-extension in 1000 Mbps half-duplex mode
• IEEE 802.3x flow-control for full-duplex operation
• Variety of flexible address filtering modes
• Detection of too long or too short packets (configurable length limits)
• Supports transmission and reception of packets that are bigger than standard packets (up to 16-Kbyte)
• Complete status for TX/RX packets
• IEEE 802.3-2002 Media Independent Interface (MII) and Gigabit Media Independent Interface (GMII)
• MDIO Master interface for PHY device configuration and management
• WISHBONE SoC Interconnection Rev. B3 compliant interface
• Internal RAM for holding 128 TX/RX buffer descriptors
• Interrupt generation on all events

Deliverables

• Soft core RTL in Verilog
• Test bench in Verilog
• Engineering support

Applications

• Internet, networking and telecom

Block Diagram of the MAC 10/100/1000 Ethernet Controller IP Core

• see the entire MAC 10/100/1000 Ethernet Controller datasheet
• get in contact with MAC 10/100/1000 Ethernet Controller Supplier