Master I3C bus controller with FIFO

The DI3CM-FIFO Core incorporates all features required by the latest MIPI I3C specification. The I3C (Improved Inter Integrated Circuit) is the next generation from I2C. Keeping the best assets from its elder brother, the I3C has major improvements in use and power and performance. The Core uses just two pins and consumes a fraction of the energy, reducing cost and complexity while allowing multiple sensors from different vendors to be easily interfaced to a controller or application processor. Digital Core Design maintains backward compatibility, to enable a smooth transition from I2C to I3C and focus on simple implementation. The newest Core offers a flexible multi-drop interface between the host processor and peripheral sensors to support the growing usage of sensors in embedded systems. The same I3C standardizes sensor communication, reduces the number of physical pins used in sensor system integration and supports low-power, highspeed and other critical features that are currently covered by I2C and SPI.

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