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55nmHV MTP Non Volatile Memory for Standard CMOS Logic Process
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Memory controller (SDRAM or DDR SDRAM)
The logiMEM SDR/DDR SDRAM controller provides a powerful, yet simple-to-use interface between the industry standard memory devices and several processor or DMA devices which share the same physical memory devices and access them through the Processor Local Bus (PLB), On-Chip Peripheral Bus (OPB), Xilinx CacheLink and Xylon Memory Bus. Written in generic RTL VHDL, it is extremely adoptable and can fit into high-end SoRC (System on Reprogrammable Chip) systems, as well as into low-end systems featuring UMA (Unified Memory Architecture) system architecture.
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Memory controller - SDR SDRAM DDR SDRAM IP
- Memory controller (SDRAM or DDR SDRAM) and Arbiter
- Complete memory system supporting any combinations of SDR SDRAM, DDR, DDR2, Mobile SDR, FCRAM, Flash, EEPROM, SRAM and NAND Flash, all in one IP core
- DDR1 DDR2 SDRAM Memory Controller
- Multi-Port Memory Controller (DDR/DDR2/SDRAM)
- Avalon Multi-port SDRAM Memory Controller IP Core
- Streaming Multi-port SDRAM Memory Controller