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Memory controller (SDRAM or DDR SDRAM)
The logiMEM SDR/DDR SDRAM controller provides a powerful, yet simple-to-use interface between the industry standard memory devices and several processor or DMA devices which share the same physical memory devices and access them through the Processor Local Bus (PLB), On-Chip Peripheral Bus (OPB), Xilinx CacheLink and Xylon Memory Bus. Written in generic RTL VHDL, it is extremely adoptable and can fit into high-end SoRC (System on Reprogrammable Chip) systems, as well as into low-end systems featuring UMA (Unified Memory Architecture) system architecture.
Features
- Supports industry standard SDR and DDR SDRAM memory devices
- Supports Processor Local Bus (PLB) system interface
- Programmable system data interface speed (for DDR SDRAM only)
- Supports SDRAM data path widths of 8, 16, and 32 bits
- Little-endian connections to memory devices
- Programmable burst length that applies for both Read and Write cycles
- Supports overlapped read and write transfers
- Data masking Byte enable signals supported for Write cycles
- Programmable SDR/DDR SDRAM row and column address width
- Programmable number of SDR/DDR SDRAM chips
- Programmable SDR/DDR SDRAM timings (i.e. CAS latency)
- Supported different SDR/DDR SDRAM initialization sequences
- Automatic refresh generation with programmable refresh intervals
- Supported memory Self-refresh mode
- Supported memory Power Down mode
- Low gate count, high speed, high performance solution
- Parametrizable VHDL design that allows customization and can be tailored to fulfill your needs
- Prepared for Xilinx Platform Studio (XPS) and the EDK
Deliverables
- VHDL source code for project use
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Memory controller - SDR SDRAM DDR SDRAM
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