The M8051EW V3.0 is a highly configurable softcore implementation of the industry standard 8051 microcontroller that features a two-clocks-per-machine cycle architecture. Use of standard synchronous design methodology makes this core simple to integrate into both ASIC and FPGA SoC designs.
The M8051EW V3.0 includes many key enhancements and product updates when compared to the Mentor Graphics M8051EW+ core offered by IPextreme. All product enhancements and support services of the M8051EW offered by Syntill8, as well as design services, are provided by the original M8051EW IP architect.
Three additional peripheral cores that available for use with the M8051EW include the M2WIS (a two-wire slave interface), the M4WIS (a four-wire slave interface) and the UDPMAC (a 1Gbps Ethernet MAC with an RGMII interface).
- Binary and Memory cycle compatible with the Intel 8051•
- Optional conditional branch acceleration
- Up to eight 16-bit data pointers
- 25-input, five level interrupt controller
- Optional full implementation of legacy peripherals: 32 GPIO ports, 3 16-bit counters and full-duplex serial port Watchdog timer
- 2-wire and 4-wire master interfaces
- Pulse width modulator array
- Flexible interfacing options for external peripherals Power saving modes: powerdown, stasis, idle and run
- Fast 2-clocks per machine cycle implementation
- Richly featured hardware debugger: multiple breakpoints, instruction traceback, single step execution. Full access to all address spaces
- 1Mbyte program and data address spaces
- Memory interfaces all support wait states and may be configured for synchronous or asynchronous devices
- Optional de-multiplexed program and data interfaces
- Optional single machine cycle memory accesses
- The core RTL is highly configurable at compile time allowing users to implement only the features required by their application.
- Major configuration options include:
- Combined program and data address space or Harvard architecture
- Optional 20-bit (1Mbyte) extended memory addressing scheme with additional stack
- 1, 2, 4 or 8 16-bit data pointers
- Each memory component may use a synchronous or asynchronous interface
- Hardware multiplier/divider is optional
- Up to 25 interrupt sources with up to 5 priority levels
- All peripherals are optional and may be excluded if not required
- Debug traceback depth and number of hardware triggers are selectable
- The core includes the following configurable peripherals as standard:
- Three timer/counters
- Legacy UART
- Watchdog timer
- Two-wire master interface
- Four-wire master interface
- Pulse width modulator array, with ramping option
- All non-legacy peripherals include a configurable clock prescaler, and configurable base addresses and interrupt channels.
- The M8051EW offers three power saving states. These
- are implemented by dividing the core logic into several synchronous clock domains using optional clock gates. These reduce power consumption by 75% in the idle state and to leakage levels in the stasis and powerdown states.
- VHDL '93 and Verilog 2001 RTL source code
- RTL configuration script
- VHDL and Verilog testbenches
- Demonstration assembly code
- Simulation scripts for Modelsim and Cadence
- Synopsys synthesis compile scripts and SDC timing constraint files
- Example Mentor DFT and ATPG scripts
- Example netlist implementation with SDF files
- Detailed product specification and a user guide containing implementation notes
Block Diagram of the Mentor Graphics/Syntill8 M8051EW V3.0 Fast 8-bit Microcontroller with on-chip debug