The M8051W V5.0 is a high performance core that executes each machine cycle in two clock cycles, giving a clock-for-clock performance that is six times faster than the M8051 and M8052 cores. They remain, however, binary and memory cycle compatible with Intel MCV-51 devices.
The M8051W incorporates various extended features, such as extra data pointers, support of extra interrupts and interrupt priority levels, optional multiple clock domains for optimising power consumption and support for synchronous memory cells.
The M8051W V5.0 includes many key enhancements and product updates when compared to the Mentor Graphics M8051W+ core offered by IP-Extreme. All product enhancements and support services of the M8051W V5.0 offered by Syntill8, as well as design services, are provided by the original M8051W IP architect.
Three additional peripheral cores that available for use with the M8051W include the M2WIS (a two-wire slave interface), the M4WIS (a four-wire slave interface) and the UDPMAC (a 1Gbps Ethernet MAC with an RGMII interface).
- Binary and Memory cycle compatible with Intel 8051 Designs
- Fast 2-clocks per machine cycle implementation
- 1Mbyte program and data address spaces
- Memory interfaces may be configured for synchronous or asynchronous devices
- External interfaces support wait states
- Optional demultiplexed program and data interfaces
- Up to 8 16-bit data pointers
- 25-input, five level interrupt controller
- Full implementation of legacy peripherals: 32 GPIO ports, 3 16-bit counter timers and a full-duplex serial port. All legacy peripherals are optional
- Flexible interfacing options for external peripherals
- Power saving modes: powerdown, idle and run
- The core RTL is highly configurable at compile time allowing users to implement only the features required by their application.
- Major configuration options include:
- Combined program and data address space or Harvard architecture
- Optional 20-bit (1Mbyte) extended memory addressing scheme with additional stack
- Number of 16-bit data pointers (1, 2, 4 or 8)
- Each memory component may use a synchronous or asynchronous interface
- Hardware multiplier/divider is optional
- The number of interrupt sources (up to 25) and priority levels (up to 5)
- All peripherals are optional and may be excluded if not required
- Debug traceback depth and number of hardware triggers selectable
- The core includes the following peripherals as standard:
- Three timer/counters
- Legacy UART
- Watchdog timer
- Two-wire interface
- Four-wire interface
- Pulse width modulators, with ramping option
- All the non-legacy peripherals include a configurable clock prescaler, and have configurable base addresses and interrupt channels.
- The M8051W offers three power saving states. These are implemented by dividing the core logic into several synchronous clock domains using optional clock gates. These reduce power consumption by 75% in the idle state and to leakage levels in the stasis and powerdown states. The microcontroller can be awoken from idle and stasis states using interrupts.
- The core runs all standard 8051 binary code. Syntill8 recommends Keil C51 and IAR Systems compilers for code development. These compilers can optimise code by making use of the M8051W data pointer and interrupt extensions.
- VHDL '93 and Verilog 2001 RTL source code
- RTL configuration script
- VHDL and Verilog Testbenches
- Demonstration assembly code
- Simulation scripts for Modelsim and Cadence
- Synopsys synthesis compile scripts and SDC timing constraint files
- Example Mentor DFT and ATPG scripts
- Example netlist implementation with SDF files • Detailed product specification and a user guide containing implementation notes.
Block Diagram of the Mentor Graphics/Syntill8 M8051W V 5.0 Fast 8-bit Microcontroller