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Metal programmable ROM compiler - Memory optimized for low power - compiler range up to 256 k
Metal programmable ROM compiler - TSMC 65 nm LP - Non volatile memory optimized for low power - compiler range up to 256 k
Features
- Power reduction features
- Decrease of packaging cost
- Smaller SoC area
- Decrease of fabrication costs
- Programmable through via layer between metal layers 1 and 2
- SoC routing allowed upwards from Metal 3
- Patented High Density bit cell
- 5% to 10% denser than contenders
- Part of the High Density - Low Power Panoply
- Dual port memory array and memory register Eris
- Single port memory register Aura
- Single Port memory array Haumea
- Density and Speed optimized standard cell libraries
- Optimal Design for Yield
- Read margin optimized instance by instance
- Design methodology ensuring High-Yield circuits despite Mismatch
- Association with LDO for regulated power supply voltages
- Optional BIST for industrial fabrication test of instances
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ROM IP
- Single Port, Low Voltage, GLOBALFOUNDRIES 28SLP, HVt & Svt, ROM Memory Compiler
- Metal programmable ROM compiler - Memory optimized for low power - Dual Voltage - compiler range up to 1024 k
- Metal programmable ROM compiler - Memory optimized for low power and high density - Dual Voltage - compiler range up to 1024 k
- Metal programmable ROM compiler - Memory optimized for low power and high density - Dual Voltage - compiler range up to 1024 k
- Metal programmable ROM compiler - Memory optimized for low power - compiler range up to 1024 k
- Parameterizable ROM Built In Self Test Controller