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Configurable PCI Express 3.0, 2.0, 1.1 Controller IP for ASIC/SoC
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MicroBlaze Debug Module (MDM)
The datasheet provides the design specification for the MicroBlaze Debug Module (MDM). The MDM core enables JTAG-based debugging of one or more MicroBlaze processors.
Features
- Support for JTAG-based software debug tools
- Support for debugging up to 32 MicroBlaze processors
- Support for synchronized control of multiple MicroBlaze processors
- Support for a JTAG-based UART with a configurable AXI4-Lite interface
- Based on Boundary Scan (BSCAN) logic in Xilinx devices
- Direct JTAG-based access to memory with a configurable AXI4 master interface
- Configurable software access to debug functionality through the AXI4-Lite interface
- Support for cross-trigger between connected MicroBlaze cores, Zynq-7000 Processing System and Integrated Logic Analyzer (ILA) cores
- External trace function to funnel program trace from connected MicroBlaze cores to external interfaces
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