MIPI M-PHY HS Gear 4 IP is compliant with the MIPI serial communication protocol for use in mobile systems where performance, power, and efficiency are key criteria. It is the foundation for several upper layer protocols which manage complex data transfer functions. Each of these protocols is optimized for its particular purpose, such as data storage, data transfer, display, camera, memory sharing, and radio interface. Scalability and modularity are also important features of the MIPI M-PHY, as these features allow designers to more easily adapt to evolving system and application requirements.
Supports MIPI CSI-3, MIPI DigRF, MIPI LLI, and MIPI UniPro
• Adopted by ➢ PCI SIG for M-PCIe ➢ USB IF for SSIC
Supports Electrical Idle presentation with fast Electrical Idle Entry and Exit.
- PWM Signalling for Low Speed [LS] data
- Supports LS burst, HS burst, STALL, SLEEP, HIBERN8 states
- Clocking solution for both transceivers
- In-built reference-less oscillator to support PWM operation
- PWM decoder supports Gear 1-7 modes
- Supports squelch detection
- Supports Receiver Detect
- Compatible to the RMMI Interface
- Programmable internal/external loopback modes between Tx and Rx.
- On-chip clock generation for either transmitter or receiver
- Standby / power down mode
- Low silicon surface
Block Diagram of the MIPI 4.1 M-PHY HS Gear 4 IP IP Core