MIPI BIF Slave interface provides full support for the two-wire MIPI BIF synchronous serial interface, compatible with BIF specification. Through its BIF companilitity, it provides a simple interface to a wide range of low-cost devices. MIPI BIF Slave IIP is proven in FPGA enviroment. The host interface of the MIPI BIF can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Wishbone or Custom protocol.
MIPI BIF SLAVE IIP is supported natively in Verilog, VHDL and SystemC
- Supports 1.0 MIPI BIF Specification
- Full MIPI BIF Slave functionality
- Supports following frames
- power control
- UID search
- Device specific
- Supports Low power modes
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
- Simple interface allows easy connection to microprocessor/microcontroller devices
- SmartDV's MIPI Slave IP contains following.
- The MIPI Slave interface is available in Source and netlist products.
- The Source product is delived in plain text verilog or VHDL or SystemC source code
- Integration testbench and tests
- Scripts for simulation and synthesis with support for command EDA tools
- Documentation contains User's Guide and Release notes.
Block Diagram of the MIPI BIF Slave controller IP Core