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MIPI Compliant D-PHY
The MIPI D-PHY is compliant with the MIPI Alliance Standard for D-PHY. Although it is primarily used for connecting cameras and display devices to a cost processor, it can also be used for many other portable applications. It is used in a master-slave configuration. High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control.
Features
- Complies with MIPI Standard for D-PHY V1.0
- Point-to-point differential interface supporting multiple data lanes and a clock lane
- Supports both high speed and low-power modes
- Data lanes support both bidirectional and unidirectional modes
- Clock lane supports unidirectional communication
- 80 Mbps to 1Gbps data rate in high speed mode
- 10 Mbps data rate in low-power mode
- Modular design to allow for all possible configurations
- Low power dissipation
Deliverables
- Data Sheet/Specifications
- GDSII data base
- LVS Netlist
- Integration Guidelines
- Timing Model
- Behavioral Model
- LEF File for P&R
Block Diagram of the MIPI Compliant D-PHY IP Core
View MIPI Compliant D-PHY full description to...
- see the entire MIPI Compliant D-PHY datasheet
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MIPI D-PHY
- MIPI D-PHY TSMC 40LP eDRAM
- MIPI C-PHY V1.1 TSMC 28nm HPC+
- MIPI CSI-2 Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- MIPI D-PHY 1.5Gbps (4-lanes TX/RX, PLL Integrated) TSMC 28HPM
- MIPI D-PHY 2.0Gbps (4-lanes TX/RX, PLL integrated) TSMC 16FF+LL
- MIPI D-PHY 2.0Gbps (4-lanes RX) TSMC 16FF+LL