The MIPI CSI-2 Receiver IP is designed to provide MIPI CSI 1.01 compliant high speed serial connectivity for applications processors to corresponding camera modules in mobile platforms. Serial connectivity between this IP and an external the camera module’s CSI transmitter is implemented using 1 to 4 D-PHY lanes, depending on camera sensor resolutions and the resulting bandwidth needs. This IP connects to the D-PHY’s through the PPI interface.
Initial configuration of this IP and its associated D-PHY can be done through programmed IO over an AHB bus, however, other bus interfaces like AXI and OCP can be provided upon request.
This IP performs the data lane merging of image data received on PPI interface from D-PHY. It performs CRC and ECC checks to ensure the integrity of packet payload and header. Based on the user register settings, the IP either forwards or drops the erroneous packets. All forwarded packet payloads are then converted from byte to pixel format, decompressed and output to an external Image Signal Processor (ISP) of the applications processor’s graphics sub-system. All D-PHY Level errors, Packet Level errors and Protocol Decoding Level errors are communicated to the host from a status register.