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MIPI I3C Controllers - Dual Role Master (70016); APB I3C Slave (70002), Generic I3C Slave
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MIPI CSI-2 RX v1.1 Controller
The Cadence Receiver Controller IP for MIPI CSI-2 is a fully-verified configurable digital core compliant with MIPI Alliance Specification for Camera Serial Interface 2 version 1.3. It handles MIPI CSI-2 and SMIA CCP2 protocols, providing both serial pixel outputs for interfacing to an image signal processor (ISP) and packed data outputs for direct-to-memory applications. The Controller IP is engineered to quickly and easily integrate into any System-on-Chip (SoC) design, and to connect seamlessly to a Cadence, or third-party PPI-compliant D-PHY lane modules. It is an ideal cost-effective, low-power camera-interface solution for application processors and media processors for the mobile market.
Features
- Programmable Synchronization and Interrupt events
- Full MIPI CSI-2 data and byte-to-pixel conversion
- Compliant with MIPI CSI -2 v1.3
- Virtual Channel / Data type de-interleaving
- Packed, byte-to-pixel, multi pixel outputs
- Protocol error detection
- Supports all primary and secondary data formats
Benefits
- Full Featured and highly configurable IP core that is area-optimized for each application
- Complete solution - complementary master/slave IP
- Fully verified on FPGA
Deliverables
- Clear, readable, synthesizable Verilog RTL
- Synthesis scripts
- Sample Verification testbench with integrated BFM and monitors
- Documentation - Design Specification, Verification Specification and Test Plan
Applications
- Wireless communication equipment
- Mobile devices
- Consumer products
- Automotive Infotainment
- Internet of Things Products
- Internet of Things Sensors
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CSI-2
- MIPI D-PHY Compliant With CSI-2 And DSI
- MIPI CPHY DPHY Combo PHY IP on TSMC 16FF/12FF
- MIPI CSI-2 Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- MIPI CSI-2 Tansmitter v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- MIPI D-PHY / C-PHY Combo IP for TSMC 22nm
- MIPI CSI-2 TX v1.1 Controller