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MIPI CSI-2 RX v1.1 Controller
The Cadence Receiver Controller IP for MIPI CSI-2 is a fully-verified configurable digital core compliant with MIPI Alliance Specification for Camera Serial Interface 2 version 1.3. It handles MIPI CSI-2 and SMIA CCP2 protocols, providing both serial pixel outputs for interfacing to an image signal processor (ISP) and packed data outputs for direct-to-memory applications. The Controller IP is engineered to quickly and easily integrate into any System-on-Chip (SoC) design, and to connect seamlessly to a Cadence, or third-party PPI-compliant D-PHY lane modules. It is an ideal cost-effective, low-power camera-interface solution for application processors and media processors for the mobile market.
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CSI-2 IP
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- MIPI C-PHY-D-PHY Combo PHY IP on TSMC 28nm HPC+
- MIPI C-PHY/D-PHY Combo IP Universal, 4.5Gsps/4.5Gbps in TSMC 22ULP
- MIPI C-PHY V1.1 TSMC 28nm HPC+