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MIPI CSI-2 RX v1.1 Controller
The Cadence Receiver Controller IP for MIPI CSI-2 is a fully-verified configurable digital core compliant with MIPI Alliance Specification for Camera Serial Interface 2 version 1.3. It handles MIPI CSI-2 and SMIA CCP2 protocols, providing both serial pixel outputs for interfacing to an image signal processor (ISP) and packed data outputs for direct-to-memory applications. The Controller IP is engineered to quickly and easily integrate into any System-on-Chip (SoC) design, and to connect seamlessly to a Cadence, or third-party PPI-compliant D-PHY lane modules. It is an ideal cost-effective, low-power camera-interface solution for application processors and media processors for the mobile market.
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CSI-2 IP
- MIPI CSI-2 Controller Core V2
- MIPI CSI-2 Controller Core
- MIPI CSI DSI C-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI CSI-2 controller Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- MIPI CSI DSI Controller - CPHY CSI-2 Transmitter v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- MIPI D-PHY / C-PHY Combo IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)