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MIPI CSI-2 Transmitter IP Core
CSI-2 (Camera Serial Interface) transmitter IP core is highly configurable, synthesizable digital IP core which receives pixels from camera sensor, performs packing in form of long packets, and Short packets, and sends them via PPI interface to the Host processor. Designed for use in portable electronic devices such as media players, mobile phones, and personal assistant devices, the CSI-2 Transmitter IP core is fully compliant to MIPI Alliance's CSI standard, as well as to AMBA's AHB specification.
This IP core has been designed and verified using Cadence state-of-the-art EDA tools, methodology and recommended design and verification flow.
This IP core has been designed and verified using Cadence state-of-the-art EDA tools, methodology and recommended design and verification flow.
Features
- Highly configurable - 35 registers
- ~40 different maskable interrupts
- Supports up to 4 data lanes (minimum is one data lane) and one clock lane
- Supports up to 4 virtual channels
- All types of Data Interleaving are supported
- Supports up to 4 cameras
- Support both High Speed, Low Power and Ultra Low Power modes
- Various pixel formats defined in CSI protocol version 1.01 (YUV420 8-bit, YUV420 8-bit (legacy), YUV420 10-bit, YUV422 10-bit, YUV420 8-bit (CSPS), YUV420 10-bit (CSPS), YUV422 8-bit, YUV422 10-bit, RGB888, RGB666, RGB565, RGB555, RGB444,RAW6, RAW7,RAW8, RAW10, RAW12, RAW14. Other formats can be supported upon request
- Generic short Packet Data Types
- User Defined Long Packets
- ECC and CRC generation
- Fully synchronous design
Benefits
- Configurable silicon proven IP core
- Can be offered with silicon proven MIPI D-PHY
Deliverables
- Verilog source code
- Complete documentation and integration spec
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