MIPI CSI-2 Transmitter interface provides full support for the two-wire MIPI CSI2 serial interface, compatible with MIPI CSI 2 Bus Specification version 2.1. It is typically residing in a camera module and provides communication to MIPI CSI-2 receiver in an image application processor over the serial PHY link. MIPI CSI-2 Transmitter IIP is fully configurable and proven in FPGA environment. The host interface of the MIPI CSI-2 can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom bus protocol.
- Implemented in Unencrypted Verilog, VHDL and SystemC
- Supports 1.x and 2.x MIPI DSI and MIPI DSI 2 Specification.
- Supports 2.5G+ Gbits at 1 to 8 Lanes of DPHY
- Supports 2.5G+ Gbits at 1 to 4 Lanes of CPHY
- Full MIPI CSI2 Transmit and Receive core functionality
- Supports all data types
- Supports MIPI DBI specification
- Supports MIPI DCS specification
- Supports all types of D-PHY short packets
- Supports all types of D-PHY long packets
- Supports all types of C-PHY short packets
- Supports all types of C-PHY long packets
- Supports display stream compression (DSC)
- Supports all lane configuration
- Supports PPI interface
- Status counters for various events in bus.
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
- Simple interface allows easy connection to microprocessor/microcontroller devices
- Single Site license option is provided to companies designing in a single site.
- Multi Sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- The MIPI CSI-2 Transmitter interface is available in Source and netlist products
- The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases
- Lint, CDC, Synthesis, Simulation Scripts with waiver files
- IP-XACT RDL generated address map
- Firmware code and Linux driver package
- Documentation contains User's Guide and Release notes.