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MIPI CSI-2 TX v1.1 Controller
The Cadence Transmitter Controller IP for MIPI CSI-2 is a fully-verified configurable digital core compliant with MIPI Alliance Specification for Camera Serial Interface 2 version 1.1.
It provides a standard, low-power, high-speed interface, and supports all primary and secondary data types defined by MIPI CSI-2.
The Controller IP is engineered to quickly and easily integrate into any System-on-Chip (SoC) design, and to connect seamlessly to a Cadence, or third-party PPI-compliant D-PHY lane modules. The Cadence Transmitter Controller IP for MIPI CSI-2 IP is an ideal cost-effective, low-power solution to provide a high-speed serial interface between an application or image processor and MIPI CSI-2 compliant camera sensor.
It provides a standard, low-power, high-speed interface, and supports all primary and secondary data types defined by MIPI CSI-2.
The Controller IP is engineered to quickly and easily integrate into any System-on-Chip (SoC) design, and to connect seamlessly to a Cadence, or third-party PPI-compliant D-PHY lane modules. The Cadence Transmitter Controller IP for MIPI CSI-2 IP is an ideal cost-effective, low-power solution to provide a high-speed serial interface between an application or image processor and MIPI CSI-2 compliant camera sensor.
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CSI-2 IP
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- MIPI C-PHY-D-PHY Combo PHY IP on TSMC 28nm HPC+
- MIPI C-PHY/D-PHY Combo IP Universal, 4.5Gsps/4.5Gbps in TSMC 22ULP
- MIPI C-PHY V1.1 TSMC 28nm HPC+