English
You are here:
MIPI CSI2 rev 2.0 transmitter/controller for FPGA, with 8 lanes and 2.5Gbps per lane
The SVTPlus-CSI2-F is a second generation MIPI CSI2-Tx transmitter IP core for FPGA implementations. It complies with MIPI® CSI2 V2.0 and DPHY1.2 specifications, with up to 8 data lanes, at up to 2.5GBPS per lane. Total available bit rate is 20Gbps, supporting, for example, 7680x4320 (8K) images at 60fps
View MIPI CSI2 rev 2.0 transmitter/controller for FPGA, with 8 lanes and 2.5Gbps per lane full description to...
- see the entire MIPI CSI2 rev 2.0 transmitter/controller for FPGA, with 8 lanes and 2.5Gbps per lane datasheet
- get in contact with MIPI CSI2 rev 2.0 transmitter/controller for FPGA, with 8 lanes and 2.5Gbps per lane Supplier
MIPI CSI2 IP
- MIPI D-PHY Receiver in TSMC 28nm HPM
- MIPI D-PHY CSI-2 TX in GlobalFoundries 22FDX
- MIPI® CSI-2 SLAVE D-PHY IP
- MIPI C-PHY CSI-2 TX+ for TSMC 40ULP
- MIPI C-PHY/D-PHY Combo IP CSI-2 TX+, 3.5Gsps/2.5Gbps
- Very compact (500 LUTs) Camera Sensor Receiver Interface Converting from MIPI CSI-2 to AXI4-Stream Video Standard