The Cadence IP for MIPI D-PHY is a silicon proven, mixed-signal design IP, implemented on GF 65LPe processes. It is engineered to quickly and easily integrate into any design, and to connect seamlessly to a Cadence, or third-party, PPI compliant controller. The IP is implemented with a modular architecture, which allows a single clock lane to work with up to four data lanes in each. It is developed and has been extensively validated to reduce development risk and speed up time to market. This PHY IP is a cost-effective, low-power solution for demanding mobile applications.
Integration functionality is the phrase for today’s leading-edge mobile devices that contain solutions enabling growing volumes of content and video, more ways to control and interact, and longer battery life usage. Developed and available early in the life-cycle of the most advanced semiconductor process nodes, the D-PHY IP is designed to be robust under varying signal strength and noise conditions.