MIPI D-PHY 1.5Gbps (4-lanes TX/RX, PLL Integrated) TSMC 28HPM

The IP for MIPI D-PHY is compliant with the MIPI Alliance Specification for D-PHY, version 1.1, and is implemented as a separate transmitter and receiver blocks that support high-speed (HS) and low-speed (LS) signaling. Transfer speeds up to 1.5Gbps per lane in HS mode and up to 10Mbps in LS mode are supported. The receiver block also supports low-power contention detection (LP-CD).
The Cadence IP for MIPI D-PHY is flexible, low-cost, high-speed serial interface solution designed to interconnect components inside a mobile device. Design IP for MIPI D-PHY extends the interface bandwidth, enabling more advanced applications with very low power consumption through differential signaling schemes.

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