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Dual thread, superscalar, embedded 32-bit RISC-V core with 9-stage pipeline
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MIPI D-PHY 4 Lane CSI2-TX 1.2G
The MXL-DPHY-CSI2-TX is a high-frequency low-power, low-cost, source synchronous, Physical Layer supporting the MIPI Alliance Standard for D-PHY. The IP is configured as a MIPI master optimized for camera interface applications (CSI-2).
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed data traffic while low power functions are mostly used for control.
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed data traffic while low power functions are mostly used for control.
Features
- Consists of 1 Clock lane and up to 4 Data lanes
- Supports MIPI Standard 1.2 for D-PHY
- Supports both high speed and low-power modes
- 80 Mbps to 1.2Gbps data rate in high speed mode
- 10 Mbps data rate in low-power mode
- High Speed Serializer included
- Low power dissipation
Benefits
- Comprehensive embedded DFT features for allowing cost-effective high-volume manufacturing tests
Deliverables
- Datasheet
- GDSII and LVS Netlist
- LIB & LEF
- Integration Guideline
- Timing Model and Behavioral Model
- Physical Verification Report
- RTL
- One year support
Applications
- Consumer electronics
- Automotive
- IoT
- Sensor
- Camera
Block Diagram of the MIPI D-PHY 4 Lane CSI2-TX 1.2G
Video Demo of the MIPI D-PHY 4 Lane CSI2-TX 1.2G
We demonstrate our customer demo, the Teledyne e2v Snappy 2M CMOS Image Sensor, featuring Mixel D-PHY CSI-2 TX IP.
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