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OTP/eMTP: 8K - 512Kbit NVM in 65nm Standard Logic CMOS process
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MIPI D-PHY CSI-2 Receiver
The MXL-DPHY-CSI2-RX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Specification for D-PHY v1.1.
The IP is configured as a MIPI Slave optimized for CSI-2SM (Camera Serial Interface) applications.
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed data traffic while low power functions are mostly used for control.
The IP is configured as a MIPI Slave optimized for CSI-2SM (Camera Serial Interface) applications.
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed data traffic while low power functions are mostly used for control.
Features
- Consists of 1 Clock lane and up to 4 Data lanes
- Supports MIPI® Alliance Specification for D-PHY Version 1.1
- Supports both high speed and low-power modes
- 80 Mbps to 1.5 Gbps data rate in high speed mode
- 10 Mbps data rate in low-power mode
- High Speed Deserializers included
- Low power dissipation
- Testability support
- Optional resistance termination calibrator
Deliverables
- Data Sheet
- GDSII
- LVS Netlist
- Integration Guidelines
- Synopsis timing Model
- Behavioral Model
- LEF File for P&R
Applications
- Mobile
- IoT
- Display
- Camera
- Virtual Reality
- Augmented Reality
Block Diagram of the MIPI D-PHY CSI-2 Receiver IP Core
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