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eUSB 3.1 Gen 2 Device Controller - Software Enumeration, FIFO Interface
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MIPI D-PHY CSI-2 TX 2.5Gbps/lane
The MXL-D-PHY-CSI2-TX-T-65LP is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for D-PHY v2.1. The PHY can be configured as a MIPI Master supporting camera interface CSI-2. The PHY supports mobile, IoT, virtual reality, and automotive applications.
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Block Diagram of the MIPI D-PHY CSI-2 TX 2.5Gbps/lane
DPHY IP
- MIPI D-PHY in TSMC (40nm, 28nm, 16nm, 12nm, 7nm)
- MIPI CSI-2 Transmitter v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- MIPI C-PHY/D-PHY Combo IP 4.5Gsps/4.5Gbps in TSMC N5
- MIPI D-PHY DSI/CSI Transmitter IP (Silicon proven in TSMC 22ULP)
- MIPI C-PHY/D-PHY Combo IP 4.5Gsps/4.5Gbps in TSMC N5
- MIPI D-PHY / C-PHY Combo IP for TSMC 22nm