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MIPI D-PHY CSI-2 TX+ in TSMC 28nm HPC+
The MXL-DPHY-CSI2-TX+ is a high-frequency low-power, source-synchronous, physical layer supporting the MIPI Alliance Specification for D-PHY v2.1, which is backward compatible with MIPI Specification for D-PHY v1.2. The PHY is configured as a MIPI master supporting Camera Serial interface CSI-2 v1.3. The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed data traffic while low power functions are mostly used for control.
Features
- Supports MIPI Specification for D-PHY Version 2.1
- Consists of 1 Clock lane and 4 Data lanes
- Supports both high speed and low-power modes
- 80 Mbps to 2.5 Gbps data rate in high speed mode
- 10 Mbps data rate in low-power mode
- Low power dissipation
- Testability support
Deliverables
- Datasheet
- GDSII and LVS Netlist
- LIB & LEF
- Integration Guideline
- Timing Model and Behavioral Model
- Physical Verification Report
- RTL
- One year support
Applications
- Automotive
- Mobile
- IoT
- Consumer Electronics
- VR
- AR
Block Diagram of the MIPI D-PHY CSI-2 TX+ in TSMC 28nm HPC+
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