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MIPI D-PHY CSI Transmitter in TSMC 28nm HPC+
The MXL-DPHY-CSI2-TX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Standard for D-PHY. The IP is configured as a MIPI master optimized for camera interface applications (CSI-2).
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed data traffic while low power functions are mostly used for control.
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed data traffic while low power functions are mostly used for control.
Features
- Consists of 1 Clock lane and up to 4 Data lanes
- Supports MIPI Standard 1.1 for D-PHY
- Supports both high speed and low-power modes
- 80 Mbps to 1.5Gbps data rate in high speed mode
- 10 Mbps data rate in low-power mode
- High Speed Serializers included
- Low power dissipation
Benefits
- Area and performance optimized for CSI-2 TX applications
Deliverables
- Datasheet
- GDSII and LVS Netlist
- Integration Guideline
- Timing Model and Behavioral Model
- One year support
- Platform optional
Applications
- IoT
- Automotive
- Virtual Reality
Block Diagram of the MIPI D-PHY CSI Transmitter in TSMC 28nm HPC+
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MIPI D-PHY
- MIPI CPHY DPHY Combo PHY IP on TSMC 16FF/12FF
- MIPI CSI-2 Tansmitter v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- MIPI D-PHY / C-PHY Combo IP for TSMC 22nm
- MIPI D-PHY 1.5Gbps (4-lanes TX/RX, PLL Integrated) TSMC 28HPM
- MIPI D-PHY 2.0Gbps (4-lanes TX/RX, PLL integrated) TSMC 16FF+LL
- MIPI D-PHY 2.0Gbps (4-lanes TX, PLL integrated) TSMC 16FF+LL