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MIPI D-PHY CSI Transmitter - TSMC, 65LP
The MXL-DPHY-CSI2-TX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Standard for D-PHY.
The IP is configured as a MIPI master optimized for camera interface applications (CSI-2).
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed data traffic while low power functions are mostly used for control.
The IP is configured as a MIPI master optimized for camera interface applications (CSI-2).
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed data traffic while low power functions are mostly used for control.
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Block Diagram of the MIPI D-PHY CSI Transmitter - TSMC, 65LP
Video Demo of the MIPI D-PHY CSI Transmitter - TSMC, 65LP
We demonstrate our customer demo, the Microsoft Azure Kinect DK, featuring the Mixel MIPI D-PHY CSI-2 TX IP.
MIPI D-PHY IP
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- MIPI D-PHY DSI/CSI Transmitter IP (Silicon proven in TSMC 22ULP)
- MIPI CSI-2 Transmitter v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- MIPI C-PHY-D-PHY Combo PHY IP on TSMC 28nm HPC+
- MIPI C-PHY and D-PHY Combo
- MIPI Universal D-PHY IP - 4.5Gbps/lane, MIPI D-PHY v2.5 Compliant