English
UFS 3.0 Host Controller with AES Encryption compatible with M-PHY 4.0 and UniPro 1.8
You are here:
MIPI D-PHY CSI Transmitter - TSMC, 65LP
The MXL-DPHY-CSI2-TX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Standard for D-PHY.
The IP is configured as a MIPI master optimized for camera interface applications (CSI-2).
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed data traffic while low power functions are mostly used for control.
The IP is configured as a MIPI master optimized for camera interface applications (CSI-2).
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed data traffic while low power functions are mostly used for control.
Features
- Consists of 1 Clock lane and up to 4 Data lanes
- Supports MIPI Standard 1.1 for D-PHY
- Supports both high speed and low-power modes
- 80 Mbps to 1.5Gbps data rate in high speed mode
- 10 Mbps data rate in low-power mode
- High Speed Serializers included
- Low power dissipation
Deliverables
- Datasheet
- GDSII and LVS Netlist
- Integration Guideline
- Timing Model and Behavioral Model
- RTL
- One year support
Block Diagram of the MIPI D-PHY CSI Transmitter - TSMC, 65LP
View MIPI D-PHY CSI Transmitter - TSMC, 65LP full description to...
- see the entire MIPI D-PHY CSI Transmitter - TSMC, 65LP datasheet
- get in contact with MIPI D-PHY CSI Transmitter - TSMC, 65LP Supplier