MIPI D-PHY CSI2-TX 4 Lane for TSMC 65nm
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for high-Speed data traffic while low power functions are mostly used for control. The embedded PLL is highly integrated and requires no external components. The PLL incorporates a lock detector, one independent output divider and supports full power down modes. Differential circuit techniques are employed to attain low jitter in the noisy environment typical of multi-million gates digital chip. The circuit is designed in a modular fashion and desensitized to process variations.
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Block Diagram of the MIPI D-PHY CSI2-TX 4 Lane for TSMC 65nm
MIPI IP
- Northwest Logic MIPI Testbench from Rambus
- MIPI D-PHY in TSMC (40nm, 28nm, 16nm, 12nm, 7nm)
- MIPI M-PHY in TSMC (28nm, 16nm, 12nm, 10nm)
- MIPI I3C Controllers - Dual Role Master (70016); APB I3C Slave (70002), Generic I3C Slave
- MIPI D-PHY DSI/CSI Transmitter IP (Silicon proven in TSMC 22ULP)
- MIPI CSI-2 Transmitter v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.