MIPI D-PHY CSI2-TX 4 Lane for TSMC 65nm
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for high-Speed data traffic while low power functions are mostly used for control. The embedded PLL is highly integrated and requires no external components. The PLL incorporates a lock detector, one independent output divider and supports full power down modes. Differential circuit techniques are employed to attain low jitter in the noisy environment typical of multi-million gates digital chip. The circuit is designed in a modular fashion and desensitized to process variations.
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Block Diagram of the MIPI D-PHY CSI2-TX 4 Lane for TSMC 65nm
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