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Compact RISC-V Processor - 32 bit, 3-stage pipeline, 32 registers
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MIPI D-PHY DSI Receiver for Automotive
The MXL-DPHY-DSI-RX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Specification for D-PHY v1.1.
The IP is configured as a MIPI Slave optimized for DSISM (Display Serial Interface) applications.
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed data traffic while low power functions are mostly used for control.
The IP is configured as a MIPI Slave optimized for DSISM (Display Serial Interface) applications.
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed data traffic while low power functions are mostly used for control.
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Block Diagram of the MIPI D-PHY DSI Receiver for Automotive
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