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MIPI D-PHY DSI Receiver
The MXL-PHY-DSI-RX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY. The IP is configured as a MIPI slave and consists of 3 lanes: 1 Clock lane and 2 data lanes, which makes it suitable for display interface applications (DSI). The High-Speed signals have a low voltage
swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control.
swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control.
Features
- Consists of 1 Clock lane and 2 Data lanes
- Complies with MIPI Standard 1.0 for D-PHY
- Supports both high speed and low-power modes
- 80 Mbps to 1Gbps data rate in high speed mode
- 10 Mbps data rate in low-power mode
- High Speed Serializer and Deserializers included
- Include circuitry for production test
- Low power dissipation
Deliverables
- Data Sheet/Specifications
- GDSII data base
- LVS Netlist
- Integration Guidelines
- Timing Model
- Behavioral Model
- LEF File for P&R
- RTL
Video Demo of the MIPI D-PHY DSI Receiver IP Core
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