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Configurable, wide-range, high-bandwidth, low-jitter phase locked-loop
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MIPI D-PHY in SMIC (40nm, 28nm)
The demand for advanced multimedia features is pushing device manufacturers to integrate more advanced peripherals such as multi-megapixel cameras and larger screens. Integrating these capabilities into next-generation devices brings new challenges to the industry in terms of power, time-to-market and overall system costs.
To address these challenges, the Mobile Industry Processor Interface (MIPI®) Alliance defines and promotes open interface specifications, such as the Camera Serial Interface (CSI-2), Display Serial Interface (DSI), which all use the MIPI D-PHY.
As a leading provider of interface IP, Synopsys’ high-quality, silicon-proven DesignWare D-PHY IP is available today in advanced process technologies.
To address these challenges, the Mobile Industry Processor Interface (MIPI®) Alliance defines and promotes open interface specifications, such as the Camera Serial Interface (CSI-2), Display Serial Interface (DSI), which all use the MIPI D-PHY.
As a leading provider of interface IP, Synopsys’ high-quality, silicon-proven DesignWare D-PHY IP is available today in advanced process technologies.
Features
- Compliant with the latest MIPI D-PHY specification, the IP in master, Tx, Rx or slave configurations is a fully verified macro that includes all analog and digital circuitry. The standard configuration includes a clock lane and two or four data lanes, each supporting a maximum of 2.5 Gbps in high-speed modes. The DesignWare MIPI D-PHY IP supports multiple low-power modes, including shut-down, and provides multiple test modes for increased reliability. It implements the MIPI recommended PPI to ensure ease of integration with the protocol controller layer.
- The DesignWare MIPI D-PHY IP provides a high-reliability, high-speed differential interface, reducing line count and minimizing cable wires and EMI shielding requirements.
Benefits
- Compliant with the MIPI D-PHY specification, v1.2
- Fully integrated hard macro
- Up to 2.5 Gbps per lane
- Aggregate throughput up to 10 Gbps in 4 data lanes
- Supports PHY Protocol Interface (PPI)
- Low-power escape modes and ultra low-power state modes
- Shutdown mode
- SCAN and loopback BIST modes
- Extensive access to internal programmability registers
- Master, slave, Tx and Rx-only configurations
- Attachable PLL for master applications
- Flexible input clock reference
- 50% DDR output clock duty cycle
- Silicon-proven, robust design available in advanced process technologies
Deliverables
- Databook
- Behavioral model
- LEF file
- .LIB file
- GDSII Layout Database
Applications
- CSI-2 Host
- DSI Host
- CSI-2 Device
- DSI Device
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