English
You are here:
MIPI D-PHY Receiver in SMIC 130nm
The MXL-PHY-DSI-RX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Standard for D-PHY.
The IP is configured as a MIPI slave and consists of 5 lanes: 1 Clock lane and 4 data lanes, which makes it suitable for camera interface applications (CSI2) and Display Serial Interface applications (DSI).
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control.
The IP is configured as a MIPI slave and consists of 5 lanes: 1 Clock lane and 4 data lanes, which makes it suitable for camera interface applications (CSI2) and Display Serial Interface applications (DSI).
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control.
View MIPI D-PHY Receiver in SMIC 130nm full description to...
- see the entire MIPI D-PHY Receiver in SMIC 130nm datasheet
- get in contact with MIPI D-PHY Receiver in SMIC 130nm Supplier
MIPI D-PHY IP
- MIPI D-PHY in TSMC (40nm, 28nm, 16nm, 12nm, 7nm)
- MIPI D-PHY DSI/CSI Transmitter IP (Silicon proven in TSMC 22ULP)
- MIPI CSI-2 Transmitter v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- MIPI C-PHY-D-PHY Combo PHY IP on TSMC 28nm HPC+
- MIPI C-PHY and D-PHY Combo
- MIPI D-PHY Universal Lane 16FFC IP for Automotive