MIPI D-PHY Receiver in SMIC 130nm

The MXL-PHY-DSI-RX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Standard for D-PHY.

The IP is configured as a MIPI slave and consists of 5 lanes: 1 Clock lane and 4 data lanes, which makes it suitable for camera interface applications (CSI2) and Display Serial Interface applications (DSI).

The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control.

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