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MIPI D-PHY Receiver in SMIC 130nm
The MXL-PHY-DSI-RX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Standard for D-PHY.
The IP is configured as a MIPI slave and consists of 5 lanes: 1 Clock lane and 4 data lanes, which makes it suitable for camera interface applications (CSI2) and Display Serial Interface applications (DSI).
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control.
The IP is configured as a MIPI slave and consists of 5 lanes: 1 Clock lane and 4 data lanes, which makes it suitable for camera interface applications (CSI2) and Display Serial Interface applications (DSI).
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control.
Features
- Consists of 1 Clock lane and 4 Data lanes
- Supporting the MIPI Standard 1.1 for D-PHY
- Supports both high speed and low-power modes
- 80 Mbps to 1.0Gbps data rate in high speed mode
- 10 Mbps data rate in low-power mode
- High Speed Deserializers included
- Low power dissipation
Deliverables
- Data Sheet
- GDSII data base
- LVS Netlist
- Timing Model
- Integration Guidelines
- Behavioral Model
- LEF File for P&R
- RTL
- One year support
- Platform (Optional)
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