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MIPI D-PHY Receiver
The MXL-DPHY-CSI2-RX is a high- frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI® Alliance Standard for D-PHY. The IP is configured as a MIPI slave optimized for camera interface applications; CSI-2.
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control.
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control.
Features
- Consists of 1 Clock lane and up to 4 Data lanes
- MIPI DPHY V1.1 specifications
- Supports both high speed and low-power modes
- 80 Mbps to 1.5 Gbps data rate in high speed mode
- 10 Mbps data rate in low-power mode
- High Speed Deserializers included
- Low power dissipation
Deliverables
- Specifications
- GDSII
- LVS netlist
- LEF file
- Verilog Model
- Timing Model
- Integration Guidlines
- RTL
- Documentation
- One year support
Block Diagram of the MIPI D-PHY Receiver IP Core
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