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MIPI D-PHY Rx IP, Silicon Proven in TSMC 28HPC+
The MIPI D-PHY Analog RX IP Core complies exactly with version 1.2 of the D-PHY specification. The Display Serial Interface (DSI) and MIPI Camera Serial Interface (CSI-2) protocols are supported. One clock lane and four data lanes make up this RX PHY.
The D-PHY comprises of a digital back end to control the I/O operations and an analogue front end to produce and receive electrical level signals. Automatically calibrated internal termination resistor.
The D-PHY comprises of a digital back end to control the I/O operations and an analogue front end to produce and receive electrical level signals. Automatically calibrated internal termination resistor.
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Block Diagram of the MIPI D-PHY Rx IP, Silicon Proven in TSMC 28HPC+
MIPI DPHY Rx IP
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