MIPI D-PHY Rx IP, Silicon Proven in UMC 55LP

The MIPI D-PHY Analog RX IP Core completely complies with the D-PHY specification, version 1.2. The Display Serial Interface (DSI) and MIPI Camera Serial Interface (CSI-2) protocols can be utilized. Four data lanes and one clock lane make up this RX PHY's configuration. The D-PHY consists of a digital back end for controlling I/O operations and an analogue front end for producing and receiving electrical level signals. The intrinsic resistor is automatically terminated.

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