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Scalable multicore architecture for a range of macrocells, small cells, cloud-RAN, DFE/DPD/ and more
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MIPI D-PHY/sub-LVDS combo Transmitter 1.5G/1.0Gbps 4-Lane
The CL12661K4T1AM2JIP is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to Host System. The CL12661K4T1AM2JIP is designed to support data rate in excess of maximum 1.5Gbps utilizing sub-LVDS / MIPI-DPHY interface specification. The CL12661K4T1AM2JIP can change Interface type to same PAD for changing mode.
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CAMERA IP
- Very compact (500 LUTs) Camera Sensor Receiver Interface Converting from MIPI CSI-2 to AXI4-Stream Video Standard
- Camera SLVS-EC v.2.0 5.0Gbps / MIPI D-PHY v2-1 4.5Gbps combo Receiver 4-Lane
- Camera MIPI D-PHY Receiver 4.5Gbps 4-Lane
- Camera capture unit for multi-camera systems
- MIPI CSI2 Receiver Interface
- MIPI CSI-2 Transmitter IP Core