The MIPI D-PHY Transmitter is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY.
The IP can be configured as a MIPI master or slave and consists of 5 lanes: 1 Clock lane and 4 data lanes.
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control.
- Consists of 1 Clock lane and 4 Data lanes
- Complies with MIPI Standard 1.1 for D-PHY
- Supports both high speed and low-power modes
- 80 Mbps to 1.0/1.5 Gbps data rate in high speed mode
- 10 Mbps data rate in low-power mode
- High Speed Serializer and De-Serializer included
- Low Power dissipation
- Data Sheet
- GDSII data base
- LVS Netlist
- Integration Guidelines
- Timing Model
- Behavioral Model
- LEF File for P&R
- One year support
- Platform (optional)
Block Diagram of the MIPI D-PHY Transmitter - Designed for TSMC 40nmLP for Automotive