32-Bit RISC-V Embedded Processor and Subsystem, Maps ARM M-0 to M-4. Optimal PPA,
MIPI D-PHY Tx IP, Silicon Proven in SMIC 55LL
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Block Diagram of the MIPI D-PHY Tx IP, Silicon Proven in SMIC 55LL
DPHY IP in SMIC IP
- MIPI D-PHY Bidirectional 2 Lanes in SMIC (40nm)
- MIPI D-PHY Bidirectional 4 Lanes in SMIC (40nm, 28nm)
- MIPI D-PHY Rx-Only 2 Lanes in SMIC (40nm)
- MIPI D-PHY Rx-Only 4 Lanes in SMIC (40nm, 28nm)
- MIPI D-PHY Tx-Only 4 Lanes in SMIC (28nm)
- Camera sub-LVDS/mini-LVDS/LVDS/HiSPi(SLVS-400, HiVCM)/MIPI-DPHY/CMOS 6-7mode Combo-Receiver 1.5Gbps