MIPI D-PHY Tx IP, Silicon Proven in TSMC 16FFC

The MIPI D-PHY Analog TX IP Core fully complies with the D-PHY specification, version 1.2. It is compatible with both the Display Serial Interface and the MIPI Camera Serial Interface (CSI-2) (DSI protocols). This TX PHY consists of one clock lane and four data lanes. Electrical level signals are produced and received by an analogue front end, while I/O activities are managed by a digital back end. internally placed auto-calibrating termination resistor The MIPI DSI PHY consists of the D-PHY, which can be used as a GPIO bank with a 5V tolerance, a PLL, a Clock Lane, four Data Lanes, and a Clock Lane (MIPI TX DPHY).

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