MIPI D-PHY Tx IP, Silicon Proven in TSMC 40LP

The MIPI D-PHY Analog TX IP Core fully complies with version 1.2 of the D-PHY specification. It is compatible with the MIPI Camera Serial Interface (CSI-2) and the Display Serial Interface (DSI protocols). It is a TX PHY with one clock lane and four data lanes. The I/O activities are managed by a digital back end, while electrical level signals are generated and received by an analogue front end. internal termination resistor with auto-calibration. The D- PHY is a MIPI DSI PHY (MIPI TX DPHY) includes a D-PHY that may be used as a GPIO bank with a 5V tolerance, a PLL, a Clock Lane, four Data Lanes, and a clock lane.

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