MIPI-DPHY Receiver 1.5Gbps 1~4-Lane
Features
- Input Clock Frequency 80MHz-750MHz
- Both Edge: nput Data Rate 160Mbps-1.5Gbps
- Single Edge: Input Data Rate 80Mbps-750Mbps
- Output Clock Frequency 20MHz~187.5MHz
- MIPI Alliance Specification for DPHY v1-1 compliant
- Low Power single 1.2V (Option:1.8/2.8/3.3V)
- 200mV swing MIPI D-PHY for low EMI
- Maximum Port: Clock 1 port / Data 1-4 port
- Escape Mode / Fail-safe circuit Options (Not include Lane control circuit)
Benefits
- We uninvested form VC and other company now, so our IP can be very cheep.
- Our ASIC partner is GUC, Faraday, Megachips, Fujitsu, Toshiba, Alchip, VeriSilicon, PGC, KeyAsic.
- We can make Custom-IP from this IP.
- We are supplying circuits-macro for other IP license. And the customer can make hard-macro from circuits-macro.
Deliverables
- Datasheet
- GDSII data
- SPICE netlist for LVS
- Timing models
- LEF file
- Verilog model
- Final simulation result
- Layout layer map file
- LVS and DRC log files
- Guideline
- options:
- Circuits data
- Simulation enviloment files
- IBIS or Hspice netlist file
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