MIPI DSI-2 Controller
It is available in 64 and 32 bit core widths. The 64 bit core width can support 1-8 D-PHY data lanes (8 bit PPI) and 1-4 CPHY lanes (16 bit PPI). The 32 bit core width an support 1-4 DPHY data lanes (8 bit PPI) and 1-2 C-PHY lanes (16 bit PPI) The core implements all three layers defined by the DSI-2 standard: Pixel to Byte Packing, Low Level Protocol, and Lane Management and is fully compliant with the DSI-2 standard. Separate Host (Tx) and Peripheral (Rx) versions of the core are provided.
The core’s native interface provides an easy-to-use data and control/status packet interfaces. The data interfaces provided with optional DPI and DBI-B/C interface adapters. The core supports command and video modes and all data types. The core is delivered fully integrated and verified with the user’s target D/C-PHY. Contact Rambus for a complete list of supported PHYs.
The core is also provided with the DSI-2 Testbench which provides a DSI-2 Bus Functional Model.
Rambus offers a DSI-2 Demonstration System which includes an FPGA Board, MIPI Interface Card and MIPI Display. Contact Rambus for more information.
Rambus also provides IP Core customization services. Contact Rambus for a quote.
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