MIPI DSI Host IP Core
DSI (Display Serial Interface) defines protocol between host processor and a peripheral such as Display device, based on MIPI Alliance specifications for mobile devices interfaces, which operates with pixels and command sets specified in the DCS standard. Its purpose is to send pixels and commands to the peripheral such as Display and receives back pixel or status information from the peripheral.
View MIPI DSI Host IP Core full description to...
- see the entire MIPI DSI Host IP Core datasheet
- get in contact with MIPI DSI Host IP Core Supplier
Block Diagram of the MIPI DSI Host IP Core IP Core
MIPI DSI IP
- MIPI CSI DSI C-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI DSI Receiver Controller v1.3
- MIPI DSI Transmit Controller v1.3
- MIPI D-PHY / C-PHY Combo IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI C-PHY/D-PHY Combo TX+ IP 4.5Gsps/4.5Gbps in TSMC N5
- MIPI CSI DSI Controller - CPHY CSI-2 Transmitter v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.