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Low Latency & size Interlaken core for ASIC or FPGA, up to 1,000Gbps, 32 lanes, 112G/lane
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MIPI DSI Host IP Core
HIP 3500 is MIPI DSI Host (TX) IP core. HIP 3500 receives pixel data and commands from the host processor through AXI/AHB interface and sends data to PPI interface. HIP 3500 is highly configurable IP core allowing optimal solution for many applications based on display panel control. HIP 3500 supports the transmission in forward and reverse directions.
DSI (Display Serial Interface) defines protocol between host processor and a peripheral such as Display device, based on MIPI Alliance specifications for mobile devices interfaces, which operates with pixels and command sets specified in the DCS standard. Its purpose is to send pixels and commands to the peripheral such as Display and receives back pixel or status information from the peripheral.
DSI (Display Serial Interface) defines protocol between host processor and a peripheral such as Display device, based on MIPI Alliance specifications for mobile devices interfaces, which operates with pixels and command sets specified in the DCS standard. Its purpose is to send pixels and commands to the peripheral such as Display and receives back pixel or status information from the peripheral.
Features
- Highly configurable
- Supports up to 4 data lanes (minimum is one data lane) and one clock lane
- Supports up to 4 virtual channels
- Interrupt generation source
- Enabling of functions such as the generation and checking of ECC and checksum words, tearing effect, etc
- Accessible address space for configuration and status registers
- Image resolution: QQVGA, QCIF, QVGA, CIF, VGA, WVGA, and XVGA
- Various pixel formats defined in DSI protocol version 1.02:
- 16-bit per pixel YcbCr 4:2:2 Format
- 20-bit per pixel YcbCr 4:2:2 Format
- 24-bit per pixel YcbCr 4:2:2 Format
- 16-bit per pixel RGB Color Format (RGB 565)
- 18-bit per pixel RGB Color Format (RGB 666)
- 24-bit per pixel RGB Color Format (RGB 888)
- 12-bit per pixel YcbCr 4:2:2 Format for Even and Odd line
- Performance: high-speed, low-power
- Image refresh: optional use of frame buffer
- Compliant to the following MIPI specifications:
- DSI (Display Serial Interface) version 1.02
- DCS (Display Command Set) version 1.02
- AMBA AHB (Advanced High-Performance Bus) version 2.0 (custom interfaces are also available upon request)
- D-PHY (800 Mbps Physical Layer Device) ver sion 1.0
- Supports both command and video mode of operation
- Fully synchronous design
- Max. data rate 800 Mbps per data lane ECC verification and correction and CRC verification
- In video mode, all the regular modes should be supported
- Non-Burst with Sync Pulses
- Non-Burst with Sync Events
- Burst mode
Benefits
- Highly Configurable
- Modularized for IP reuse
- Fully synchronous
- Clearly defined clock domains
- Layered architecture
Deliverables
- Single or multi-use license
- Verilog RTL source code
- Comprehensive documentation package
- Functional specification
- Microarchitecture
- User guide
Block Diagram of the MIPI DSI Host IP Core IP Core
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