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MIPI D-PHY Transmitter - Designed for TSMC 40nmLP for Automotive
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MIPI DSI Peripheral Controller IP Core
The HIP 3510 is a highly configurable, synthesizable digital IP core, used to exchange pixels and command data between a video source (host processor) and a display
peripheral. Designed for use in portable electronic devices such as media players, mobile phones, and personal assistant devices, HIP3510 is fully compliant to MIPI
Alliance's DSI, DPI-2, and DCS standards, as well as to AMBA's AHB specification. The video data is provided from an external D-PHY using either the HS (High Speed) or LP (Low Power) reception modes via a PPI interface, then processed by the HIP 3510 logic according to the DSI and DCS specifications., The output video data stream is sent to the DPI-2 or DBI interface.
This IP core has been designed and verified using Cadence state-of-the-art EDA tools, methodology and recommended design and verification flow.
peripheral. Designed for use in portable electronic devices such as media players, mobile phones, and personal assistant devices, HIP3510 is fully compliant to MIPI
Alliance's DSI, DPI-2, and DCS standards, as well as to AMBA's AHB specification. The video data is provided from an external D-PHY using either the HS (High Speed) or LP (Low Power) reception modes via a PPI interface, then processed by the HIP 3510 logic according to the DSI and DCS specifications., The output video data stream is sent to the DPI-2 or DBI interface.
This IP core has been designed and verified using Cadence state-of-the-art EDA tools, methodology and recommended design and verification flow.
Features
- Compliant to the following MIPI specifications:
- DSI (Display Serial Interface) 1.02
- DCS (Display Command Set) 1.02
- DPI-2 (Display Pixel Interface) 2.0
- D-PHY (Physical Layer Device) 1.0
- Highly configurable
- Data lanes: between 1 and 4
- Virtual channels: between 1 and 4
- Interrupt generation source
- Enabling of functions such as the generation and checking of ECC and checksum words, etc.
- Accessible address space for configuration and status registers
- Image resolution: QQVGA, QVGA, VGA, WVGA, XVGA, Full-HD
- Pixel formats: RGB 16, 18, 24 bits, (a.k.a. RGB565, RGB666, RGB888)
- Performance: high-speed, low-power
- Supports the following interfaces:
- Host processor: AMBA AHB (Advanced High-Performance Bus)2.0. (I2C and custom interfaces are also available upon request)
- D-PHY: PPI (PHY Protocol Interface)
- Video interface: DPI
- Supports both command and video modes of operation
- Transmission packet sequences supported: burst mode, non-burst mode with sync events,non-burst mode with sync pulses
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