130nm FTP Non Volatile Memory for Standard CMOS Logic Process
MIPI HSI Controller IP Core
Three flavors of the IP are currently available, namely, with support for AHB, AXI or OCP system buses. The IP’s internal registers are accessible through programmed IO transactions, in which case the IP functions as a bus slave. All data transfers between the SoC’s system memory and HSI interface happen either in PIO mode or in DMA mode as programmed by the driver/firmware.
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Block Diagram of the MIPI HSI Controller IP Core
silicon IP IP
- Low Jitter PLL with Accurately Spaced 16-Phase Output Clocks
- Fractional-N Frequency Synthesizer PLL (3nm - 180nm)
- Bi-Directional LVDS with LVCMOS
- Ultra Low Area Frequency Synthesizer PLL (3nm - 90nm)
- 32kHz Ultra-Fast-Lock IoT PLL
- The SST SuperFlash® IP is an embedded CMOS Flash memory IP with sector/chip Erase and byte Program capability.