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MIPI HSI Controller IP Core
The MIPI HSI Controller IP Core is used to provide high bandwidth, point-to-point, MIPI HSI ver 1.0 compliant serial communication between two peers, like the cellular modem and application processor on a mobile platform, such as a smartphone or a tablet.
Three flavors of the IP are currently available, namely, with support for AHB, AXI or OCP system buses. The IP’s internal registers are accessible through programmed IO transactions, in which case the IP functions as a bus slave. All data transfers between the SoC’s system memory and HSI interface happen either in PIO mode or in DMA mode as programmed by the driver/firmware.
Three flavors of the IP are currently available, namely, with support for AHB, AXI or OCP system buses. The IP’s internal registers are accessible through programmed IO transactions, in which case the IP functions as a bus slave. All data transfers between the SoC’s system memory and HSI interface happen either in PIO mode or in DMA mode as programmed by the driver/firmware.
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Block Diagram of the MIPI HSI Controller IP Core
silicon IP IP
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