The I3C-S core implements a versatile MIPI® Improved Inter Integrated Circuit (I3C) Slave controller core suitable for any I3C bus topology & compliant with the latest MIPI I3C-BasicSM specification.
The highly featured slave-only core communicates in Single Data Rate (SDR) mode, but can tolerate High Data Rate (HDR) traffic. It can coexist and communicate with legacy I2C devices, and it can optionally be configured to operate as such in an I3C or I2C bus. The I3C-S needs no firmware support to parse and execute the broadcast or direct Common Command Codes (CCCs) relevant to I3C Basic Slaves. It can be assigned a Dynamic Address by the bus master, or use its legacy I2C static address, it supports Hot Join and is capable of generating In-Band Interrupts when directed by the host to do so.
Designed for easy integration, the I3C-S can operate in two different modes. Under normal mode, data from private I3C or legacy I2C write transfers are stored to a FIFO, and made available to the host via an APB Slave interface. In a similar way, the host provides data to be used for private I3C or legacy I2C read transfers via the core’s APB slave interface. Alternatively, the core can operate in I3C-to-AHB bridging mode, where it autonomously converts private I3C or legacy I2C transfers to ac-cesses on its AHB master port using a simple yet configurable over-I3C protocol. Under the I3C-to-AHB bridging mode, the core needs no software assistance and provides the I3C-master access to the local AHB bus, enabling remote monitoring, configuration, debug, or data exchange. The selection between normal and bridging operation modes is under software control via the core’s control register.
The highly flexible core offers synthesis-time and run-time configuration options, which allow adapting its size and behavior to the application requirements. For example, the AHB-master interface and the clock domains synchronizers can be removed at synthesis time to reduce the core’s silicon footprint. During run-time, the I3C private data and I2C traffic can be bridged to the core's AHB master interface or transferred to and from the host via the core's APB slave interface. Also, parameters defining the CCCs processing (e.g. own-address, provisional ID, acknowledge for different type CCCs), the over-I3C protocol (i.e. number address bytes, max number of data bytes), and the AHB-master port behavior (e.g AHB burst type & address wrapping) are all run-time configurable via the core’s registers.
The I3C-S core adheres to the industry’s best coding and verification practices to ensure trouble-free implementation in ASIC or FPGA technologies. Technology mapping, constraining, and scan insertion are straight-forward, as the core contains no multi-cycle or false paths, and uses only rising-edge-triggered D-type flip-flops, no tri-states, an asynchronous reset line per clock domain, and clean clock domain crossing modules. Its reliability and low risk have been proven through rigorous verification and FPGA validation.