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MIPI I3C Slave Controller IP
The Slave Controller IP for MIPI I3C – complete IP solution, fully verified on FPGA with a superior performance to simplify board design, and increase power efficiency.
Compliant with the latest MIPI I3C specification and backward compatible with I2C, the Controller IP is engineered to quickly and easily integrate into any mobile embedded system on chip (SoC) device and expand sensor communication capabilities with better power efficiency.
Rapidly increasing numbers of sensors creates new design challenges for mobile, automotive, and Internet of Things (IoT) devices. The Cadence Slave Controller IP for MIPI I3C delivers area-optimized interface IP with the low power and high performance required for leading-edge devices. It is suitable for design challenges that include significantly higher signal count and increased bandwidth requirements.
With the Slave Controller IP for MIPI I3C your customers can always be on the move, using applications with confidence and reliability.
Compliant with the latest MIPI I3C specification and backward compatible with I2C, the Controller IP is engineered to quickly and easily integrate into any mobile embedded system on chip (SoC) device and expand sensor communication capabilities with better power efficiency.
Rapidly increasing numbers of sensors creates new design challenges for mobile, automotive, and Internet of Things (IoT) devices. The Cadence Slave Controller IP for MIPI I3C delivers area-optimized interface IP with the low power and high performance required for leading-edge devices. It is suitable for design challenges that include significantly higher signal count and increased bandwidth requirements.
With the Slave Controller IP for MIPI I3C your customers can always be on the move, using applications with confidence and reliability.
Features
- Support for multiple transmission modes: Single Data Rate (SDR) and High Data Rate (HDR)
- Compliant with the latest I3C specification
- Support for I3C common command codes
- Dynamic address assignment (DAA) support
- Optional support for user generic I/O signal registers
- Support for in-band interrupts, hot-join, mastership request
- I2C legacy device support
- APB interface support for register access
- Command queue support
- Interconnect protocol
Benefits
- Superior performance to power ratio compared to established sensor interfaces - I2C, SPI
- Complete solution - complementary master/slave IP
- Fully verified on FPGA
Deliverables
- Clear, readable, synthesizable Verilog RTL
- Synthesis scripts
- Sample Verification testbench with integrated BFM and monitors
- Documentation - Design Specification, Verification Specification and Test Plan
Applications
- Mobile devices
- Consumer products
- Automotive Infotainment
- Internet of Things (IoT) Products
- Internet of Things (IoT) Sensors
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