MIPI M-PHY(DigRF v4, UFS) TX/RX + Controller
The architecture is customizable and allows support from 1 to 4 lanes for increased throughput. It is designed with ease of integration in mind. The PHY is small, low power and contains all I/Os including primary and secondary ESD.
Efficient production testing is assured through built in BIST, multiple loop back modes and Boundary scan support.
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Block Diagram of the MIPI M-PHY(DigRF v4, UFS) TX/RX + Controller

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