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MIPI M-PHY(DigRF v4, UFS) TX/RX + Controller
The INNOSILICON MIPI M-PHY transceiver is fully compatible with V1-00-00 specifications. It supports both master and slave roles in HS Gear 1~3 and LS operation. The M-PHY uses the MIPI standard M-PORTs Protocol Interface to simplify controller integration and supports DigRFv4, SSIC, and UniPro MIPI protocols.
The architecture is customizable and allows support from 1 to 4 lanes for increased throughput. It is designed with ease of integration in mind. The PHY is small, low power and contains all I/Os including primary and secondary ESD.
Efficient production testing is assured through built in BIST, multiple loop back modes and Boundary scan support.
The architecture is customizable and allows support from 1 to 4 lanes for increased throughput. It is designed with ease of integration in mind. The PHY is small, low power and contains all I/Os including primary and secondary ESD.
Efficient production testing is assured through built in BIST, multiple loop back modes and Boundary scan support.
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Block Diagram of the MIPI M-PHY(DigRF v4, UFS) TX/RX + Controller
MIPI IP
- MIPI CSI-2 Controller Core V2
- MIPI CSI-2 Controller Core
- MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- I3C Host Controller
- MIPI CSI DSI C-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI I3C Controllers - Dual Role Master (70016); APB I3C Slave (70002), Generic I3C Slave