Immortalis-G715, GPU providing ultimate mobile gaming experiences
MIPI M-PHY(DigRF v4, UFS) TX/RX + Controller
The architecture is customizable and allows support from 1 to 4 lanes for increased throughput. It is designed with ease of integration in mind. The PHY is small, low power and contains all I/Os including primary and secondary ESD.
Efficient production testing is assured through built in BIST, multiple loop back modes and Boundary scan support.
View MIPI M-PHY(DigRF v4, UFS) TX/RX + Controller full description to...
- see the entire MIPI M-PHY(DigRF v4, UFS) TX/RX + Controller datasheet
- get in contact with MIPI M-PHY(DigRF v4, UFS) TX/RX + Controller Supplier
Block Diagram of the MIPI M-PHY(DigRF v4, UFS) TX/RX + Controller

MIPI IP
- MIPI CSI-2 Controller Core V2
- MIPI D-PHY in TSMC (40nm, 28nm, 16nm, 12nm, 7nm)
- MIPI M-PHY in TSMC (28nm, 16nm, 12nm(
- MIPI CSI-2 Transmitter v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- MIPI D-PHY / C-PHY Combo IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI I3C Controllers - Dual Role Master (70016); APB I3C Slave (70002), Generic I3C Slave