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MIPI M-PHY G2 SMIC 28HK
The Cadence IP for MIPI M-PHY is a mixed-signal design IP, implemented on SMIC 28HK processes. It is engineered to quickly and easily integrate into any design, and to connect seamlessly to a Cadence, or third-party, RMMI compliant controller.
The M-PHY IP is designed to employ modular implementation with scalability for up to four lanes in one sub-link, offering great SoC flexibility. It is developed and has been extensively validated to reduce development risk and speed up time to market.
This M-PHY IP is a cost-effective, low-power solution for demanding mobile applications. Integrated functionality is the driver for today’s leading-edge mobile devices that contain solutions enabling growing volumes of content and video, more ways to control and interact, and longer battery life usage. Developed and available early in the lifecycle of the most advanced semiconductor process nodes, the M-PHY IP is designed to be robust under varying signal strength and noise conditions.
The M-PHY IP is designed to employ modular implementation with scalability for up to four lanes in one sub-link, offering great SoC flexibility. It is developed and has been extensively validated to reduce development risk and speed up time to market.
This M-PHY IP is a cost-effective, low-power solution for demanding mobile applications. Integrated functionality is the driver for today’s leading-edge mobile devices that contain solutions enabling growing volumes of content and video, more ways to control and interact, and longer battery life usage. Developed and available early in the lifecycle of the most advanced semiconductor process nodes, the M-PHY IP is designed to be robust under varying signal strength and noise conditions.
Features
- Compliant to MIPI Specification for M-PHY v2.0
- Integrated BIST capable of producing and checking PRBS, CRPAT, and CJTPAT
- Scalable up to four LANEs per SUB-LINK
- Configurable as Type-I or Type-II MODULE
- Internal and external data-path loop-back modes
- Standard RMMI interface
- Matched analog design for low LANE-to-LANE skew and maximum timing margins
- Mobile-optimized area and power
- Receiver supports terminated/unterminated operation
- Slew-rate control for reduced EMI
Benefits
- Proven design in volume production
- Scalable LANE module offer great SoC flexibility
- Extensive testability enable low risk development and fast TTM
Deliverables
- GDS II macros with abstract in LEF
- Verilog post-layout netlist
- STA scripts for use at chip or standalone PHY levels
- Liberty timing model
- SDF for back-annotated timing verification
- Verilog models of I/O pads and RTL for all PHY modules
- Verilog testbench with memory model, configuration files, and sample tests
- Complete technical documentation set
- Verification IP set up files
Applications
- Networking
- Cloud computing
- Wireless communication equipment
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MIPI M-PHY IP
- MIPI M-PHY in TSMC (28nm, 16nm, 12nm, 10nm)
- UFS 2.1 Host Controller compatible with M-PHY 3.1 and UniPro 1.6
- UFS 2.1 Device Controller compatible with MIPI M-PHY 3.1 and UniPro 1.6
- UFS 3.0 Host Controller compatible with M-PHY 4.0 and UniPro 1.8
- UFS 3.0 Host Controller with AES Encryption compatible with M-PHY 4.0 and UniPro 1.8
- MIPI D-PHY Receiver in TSMC 28nm HPM