MIPI M-PHY G2 TSMC 28HPL

Features

• Compliant to MIPI Specification for M-PHY v2.0
• Integrated BIST capable of producing and checking PRBS, CRPAT, and CJTPAT
• Scalable up to four LANEs per SUB-LINK
• Configurable as Type-I or Type-II MODULE
• Internal and external data-path loop-back modes
• Standard RMMI interface
• Matched analog design for low LANE-to-LANE skew and maximum timing margins
• Mobile-optimized area and power
• Receiver supports terminated/unterminated operation
• Slew-rate control for reduced EMI

Benefits

• Proven design in volume production
• Scalable LANE module offer great SoC flexibility
• Extensive testability enable low risk development and fast TTM

Deliverables

• GDS II macros with abstract in LEF
• Verilog post-layout netlist
• STA scripts for use at chip or standalone PHY levels
• Liberty timing model
• SDF for back-annotated timing verification
• Verilog models of I/O pads and RTL for all PHY modules
• Verilog testbench with memory model, configuration files, and sample tests
• Complete technical documentation set
• Verification IP set up files

Applications

• Networking
• Cloud computing
• Wireless communication equipment

• see the entire MIPI M-PHY G2 TSMC 28HPL datasheet
• get in contact with MIPI M-PHY G2 TSMC 28HPL Supplier