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MIPI M-PHY G3 6.0 Gbps (71151)
The Samsung Foundry MIPI M-PHY IP is a hard macro PHY for UFS protocol. IO pads and ESD structures are included with extensive built-in self test features such as loopback and scan support. It offers a cost-effective and low-power solution. It builds on silicon-proven designs that are in volume production.
Features
- 14nm low power CMOS device technology
- 1.8V, 0.85V dual power supply
- Compliant to MPHY 3.1 specification
- Supports HS-G1/HS-G2/HS-G3 Series A and B(Series A: 1.248G, 2.496G, 4.992 Gbps Series B: 1.456G, 2.912G, 5.824 Gbps)
- Supports PWM G1 to G4 (3 M to 72 Mbps)
- Channel Configuration for Data Lanes
- Common (CMN) and 2 Data Lanes
- Supports the following pre-emphasis levels
- 1.5/3/6dB
- 19.2M or 26MHz reference clock is required
- Built-in self test feature capable of producing and checking PRBS random patterns
Deliverables
- Front-end: Timing LIB, Verilog model, Sample test bench
- Back-end: Physical view LEF, GDSII layout, DRC, LVS
- Documentation : Datasheet and User’s guide
Applications
- Consumer/IoT
Block Diagram of the MIPI M-PHY G3 6.0 Gbps (71151) IP Core
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MIPI M-PHY
- MIPI M-PHY G4 Designed For TSMC 28nm HPC+
- MIPI M-PHY in TSMC (28nm, 16nm, 12nm, 10nm)
- UFS 2.1 Host Controller compatible with M-PHY 3.1 and UniPro 1.6
- UFS 2.1 Device Controller compatible with MIPI M-PHY 3.1 and UniPro 1.6
- MIPI M-PHY - TSMC 40nm
- UFS 3.0 Host Controller compatible with M-PHY 4.0 and UniPro 1.8